LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity a2of3 is
port (a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
y : out std_logic);
end a2of3;
architecture a of a2of3 is
signal g0, g1, g2 : std_logic;
begin
g0 <= a0 and a1;
g1 <= a1 and a2;
g2 <= a2 and a0;
y <= g0 or g1 or g2;
-- or just y <= (a0 and a1) or (a1 and a2) or (a2 and a0);
end;