LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity barrel is
generic(Implementation : Integer := 0);
port (
A : in std_logic_vector(15 downto 0); -- input data
ar : in std_logic; -- arithmetic
shd : in std_logic_vector( 2 downto 0); -- shift distance
Y : out std_logic_vector(15 downto 0)); -- output
end barrel;
architecture a of barrel is
signal m : std_logic;
begin
m <= ar and A(A'high); -- the new MSBit
i0: if Implementation = 0 generate
with shd select
Y <= A when "000",
m & A(A'high downto 1) when "001",
m & m & A(A'high downto 2) when "010",
m & m & m & A(A'high downto 3) when "011",
m & m & m & m & A(A'high downto 4) when "100",
m & m & m & m & m & A(A'high downto 5) when "101",
m & m & m & m & m & m & A(A'high downto 6) when "110",
m & m & m & m & m & m & m & A(A'high downto 7) when "111",
(others => 'X') when others;
end generate;
i1: if Implementation = 1 generate
process(A, shd, m)
variable s : Integer;
variable tmp : std_logic_vector(Y'range);
begin
s := conv_integer(shd);
tmp := A;
for i in 0 to 7 loop
if (i < s) then tmp := m & tmp(A'high downto 1); end if;
end loop;
Y <= tmp;
end process;
end generate;
i2: if Implementation = 2 generate
process(A, shd, m)
variable s : Integer;
begin
s := conv_integer(shd);
for i in Y'range loop
if (i > (Y'high - s)) then Y(i) <= m;
else Y(i) <= A(i+s);
end if;
end loop;
end process;
end generate;
end;