LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity bin2gray is
generic (N : Natural := 4);
port (
bin : in std_logic_vector(N-1 downto 0);
gray : out std_logic_vector(N-1 downto 0) );
end bin2gray;
architecture a of bin2gray is
begin
gray <= '0' & bin(N-1 downto 1) xor bin;
end;