LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.all; -- used only in the 3rd implementation
entity demux is
port (
I : in std_logic;
SEL : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end demux;
architecture a of demux is
begin
-- use only one of the 3 implementations!
with SEL select
Y <= I & "000" when "11",
'0' & I & "00" when "10",
"00" & I & '0' when "01",
"000" & I when "00",
(others => 'X') when others;
process(I, SEL)
begin
Y <= (others => '0');
case SEL is
when "00" => Y(0) <= I;
when "01" => Y(1) <= I;
when "10" => Y(2) <= I;
when "11" => Y(3) <= I;
when others => Y <= (others => 'X');
end case;
end process;
process(I, SEL)
begin
Y <= (others => '0');
Y(conv_integer(SEL)) <= I;
end process;
end;