LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity dff_aload is port ( clk : in std_logic; aload : in std_logic; ad : in std_logic; d : in std_logic; q : out std_logic); end dff_aload; architecture a of dff_aload is begin process(clk, aload, ad) begin if aload = '1' then q <= ad after 1 ns; elsif clk'event and clk='1' then q <= d after 1 ns; end if; end process; end;