LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity dff_set_reset is
port (
clk : in std_logic;
pre : in std_logic;
clr : in std_logic;
d : in std_logic;
q : out std_logic);
end dff_set_reset;
architecture a of dff_set_reset is
begin
process(clk, pre, clr)
begin
if pre = '1' and clr = '1' then
q <= 'X';
elsif clr = '1' then
q <= '0';
elsif pre = '1' then
q <= '1';
elsif clk'event and clk='1' then
q <= d;
end if;
end process;
end;