LIBRARY IEEE;
use IEEE.std_logic_1164.all;
entity filt_long is
generic (N : Integer := 3);
port(
clk : in std_logic;
d : in std_logic;
q : out std_logic);
end filt_long;
architecture a of filt_long is
signal counts : Integer range 0 to N-2;
signal samples : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
samples <= samples(0) & d;
if (samples(0) xor samples(1)) = '1' then -- different
counts <= N-2;
else
if counts = 0 then q <= samples(1);
else counts <= counts - 1; -- count down
end if;
end if;
end if;
end process;
end;