LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity gray_cnt is
generic (N : Natural := 4);
port (
clk : in std_logic;
sclr : in std_logic;
cnten : in std_logic;
q : out std_logic_vector(N-1 downto 0) );
end gray_cnt;
architecture a of gray_cnt is
component bin2gray is
generic (N : Natural := 4);
port (
bin : in std_logic_vector(N-1 downto 0);
gray : out std_logic_vector(N-1 downto 0) );
end component;
component reg_sclr is
generic (N : Natural := 4);
port (
clk : in std_logic;
sclr : in std_logic;
ce : in std_logic;
d : in std_logic_vector(N-1 downto 0);
q : out std_logic_vector(N-1 downto 0) );
end component;
signal cnt : std_logic_vector(N-1 downto 0);
signal gray : std_logic_vector(N-1 downto 0);
begin
process (clk)
begin
if clk'event and clk='1' then
if sclr = '1' then
cnt <= (others => '0');
cnt(0) <= '1';
elsif cnten = '1' then
cnt <= cnt + 1;
end if;
end if;
end process;
b2g: bin2gray
generic map (N => N)
port map(
bin => cnt,
gray => gray);
greg: reg_sclr
generic map(N => N)
port map(
clk => clk,
sclr => sclr,
ce => cnten,
d => gray,
q => q);
end;