LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity mov_int is
generic(Nd : Integer := 8; -- data width
Na : Integer := 2); -- 2**Na samples
port (
clk : in std_logic;
clr : in std_logic;
x : in std_logic_vector( Nd-1 downto 0); -- input data
y : out std_logic_vector(Na+Nd-1 downto 0)); -- output
end mov_int;
architecture a of mov_int is
signal diff : std_logic_vector(Nd downto 0);
signal diffe : std_logic_vector(Na+Nd-1 downto 0);
signal acc : std_logic_vector(Na+Nd-1 downto 0);
type pipe_arr is array(0 to 2**Na-1) of std_logic_vector(Nd-1 downto 0);
signal pipe : pipe_arr;
begin
diff <= ('0' & x) - ('0' & pipe(pipe'high));
process(diff)
begin
diffe <= (others => diff(Nd)); -- fill with the sign bit
diffe(Nd-1 downto 0) <= diff(Nd-1 downto 0);
end process;
process(clk) -- the accumulator
begin
if rising_edge(clk) then
if clr='1' then
acc <= (others => '0');
for i in pipe'range loop
pipe(i) <= (others => '0');
end loop;
else
acc <= acc + diffe;
pipe(0) <= x;
for i in 1 to pipe'high loop
pipe(i) <= pipe(i-1);
end loop;
end if;
end if;
end process;
y <= acc;
end;