library IEEE;
USE IEEE.STD_LOGIC_1164.all;
entity mux21nbit is
generic(N : Integer := 4; tdel : time := 2 ns);
port(A0 : in std_logic_vector(N-1 downto 0);
A1 : in std_logic_vector(N-1 downto 0);
SEL : in std_logic;
Y : out std_logic_vector(N-1 downto 0));
end mux21nbit;
architecture a of mux21nbit is
begin
with SEL select
Y <= A0 after tdel when '0',
A1 after tdel when '1',
(others => 'X') after tdel when others;
end;