LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity mux31 is
port (
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
SEL : in std_logic_vector(1 downto 0);
Y : out std_logic);
end mux31;
architecture a of mux31 is
begin
with SEL select
Y <= I2 when "10",
I1 when "01",
I0 when "00",
'-' when others;
-- this will generate more logic
-- with SEL select
-- Y <= I2 when "10",
-- I1 when "01",
-- I0 when others;
end;