library IEEE;
USE IEEE.STD_LOGIC_1164.all;
entity mux41 is
port(A0 : in std_logic_vector(5 downto 0);
A1 : in std_logic_vector(5 downto 0);
A2 : in std_logic_vector(7 downto 0);
A3 : in std_logic_vector(7 downto 0);
SEL : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(7 downto 0));
end mux41;
architecture a of mux41 is
component mux21nbit is
generic(N : Integer := 4);
port(A0 : in std_logic_vector(N-1 downto 0);
A1 : in std_logic_vector(N-1 downto 0);
SEL : in std_logic;
Y : out std_logic_vector(N-1 downto 0));
end component;
signal y01 : std_logic_vector(5 downto 0);
signal y23 : std_logic_vector(7 downto 0);
begin
m01: mux21nbit
generic map(N => 6)
port map(A0 => A0, A1 => A1, SEL => SEL(0), Y => Y01);
m23: mux21nbit
generic map(N => 8)
port map(A0 => A2, A1 => A3, SEL => SEL(0), Y => Y23);
my: mux21nbit
generic map(N => 8)
port map(A0 => "00" & Y01, A1 => Y23, SEL => SEL(1), Y => Y);
end;