LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity mux4reg is
port (
status : in std_logic_vector( 2 downto 0);
cfg1 : in std_logic_vector( 5 downto 0);
cfg2 : in std_logic_vector( 3 downto 0);
cfg3 : in std_logic_vector( 1 downto 0);
SEL : in std_logic_vector( 1 downto 0);
Y : out std_logic_vector( 7 downto 0));
end mux4reg;
architecture a of mux4reg is
begin
-- use only one of the two descriptions!
with SEL select
Y <= "000000" & cfg3 when "11",
"0000" & cfg2 when "10",
"00" & cfg1 when "01",
"00000" & status when "00",
(others => 'X') when others;
process(status, cfg1, cfg2, cfg3, SEL)
begin
Y <= (others => '0');
case SEL is
when "00" => Y(status'range) <= status;
when "01" => Y(cfg1'range ) <= cfg1;
when "10" => Y(cfg2'range ) <= cfg2;
when "11" => Y(cfg3'range ) <= cfg3;
when others => Y <= (others => 'X');
end case;
end process;
end;