library ieee;
use ieee.std_logic_1164.all;
package mypack is
subtype my_data is std_logic_vector(10 downto 0);
subtype my_int is Integer range 0 to 2047;
type my_array is array(0 to 15) of my_data;
subtype cmd_code is std_logic_vector(1 downto 0);
constant cmd_nop: cmd_code := "00";
constant cmd_wr : cmd_code := "01";
constant cmd_rd : cmd_code := "10";
constant cmd_ad : cmd_code := "11";
function se( src : std_logic_vector;
ndst : Integer) return std_logic_vector;
function psrg(sr : std_logic_vector) return std_logic;
-- (see Xilinx APP 052 July 7, 1996, ver. 1.1)
end mypack;
package body mypack is
constant cmd_dc : cmd_code := "--";
function psrg(sr : std_logic_vector) return std_logic is
variable bit0 : std_logic;
begin
case sr'length is
when 32 => bit0 := sr(31) xor sr(21) xor sr( 1) xor sr( 0);
when 31 => bit0 := sr(30) xor sr(27);
when 30 => bit0 := sr(29) xor sr( 5) xor sr( 3) xor sr( 0);
when 29 => bit0 := sr(28) xor sr(26);
when 28 => bit0 := sr(27) xor sr(24);
when 27 => bit0 := sr(26) xor sr( 4) xor sr( 1) xor sr( 0);
when 26 => bit0 := sr(25) xor sr( 5) xor sr( 1) xor sr( 0);
when 25 => bit0 := sr(24) xor sr(21);
when 24 => bit0 := sr(23) xor sr(22) xor sr(21) xor sr(16);
when 23 => bit0 := sr(22) xor sr(17);
when 22 => bit0 := sr(21) xor sr(20);
when 21 => bit0 := sr(20) xor sr(18);
when 20 => bit0 := sr(19) xor sr(16);
when 19 => bit0 := sr(18) xor sr( 5) xor sr( 1) xor sr( 0);
when 18 => bit0 := sr(17) xor sr(10);
when 17 => bit0 := sr(16) xor sr(13);
when 16 => bit0 := sr(15) xor sr(14) xor sr(12) xor sr( 3);
when 14 => bit0 := sr(13) xor sr( 4) xor sr( 2) xor sr( 0);
when 13 => bit0 := sr(12) xor sr( 3) xor sr( 2) xor sr( 0);
when 12 => bit0 := sr(11) xor sr( 5) xor sr( 3) xor sr( 0);
when 11 => bit0 := sr(10) xor sr( 8);
when 10 => bit0 := sr( 9) xor sr( 6);
when 9 => bit0 := sr( 8) xor sr( 4);
when 8 => bit0 := sr( 7) xor sr( 5) xor sr( 4) xor sr( 3);
when 5 => bit0 := sr( 4) xor sr( 2);
when 15 | 7 | 6 | 4 | 3 =>
bit0 := sr(sr'length-1) xor sr(sr'length-2);
--when 15 => bit0 := sr(14) xor sr(13);
--when 7 => bit0 := sr( 6) xor sr( 5);
--when 6 => bit0 := sr( 5) xor sr( 4);
--when 4 => bit0 := sr( 3) xor sr( 2);
when others => bit0 := '-';
end case;
return bit0;
end;
function se( src : std_logic_vector;
ndst : Integer) return std_logic_vector is
variable tmp : std_logic_vector(ndst-1 downto 0);
begin
if src'length <= ndst then
for i in src'range loop
tmp(i) := src(i);
end loop;
for i in src'high+1 to ndst-1 loop
tmp(i) := src(src'high);
end loop;
else
for i in 0 to ndst-1 loop
tmp(i) := src(i);
end loop;
end if;
return tmp;
end se;
end mypack;