LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity shift_reg_full is
generic (N : Natural := 10; del : time := 10 ns);
port (
clk : in std_logic;
rst_n : in std_logic;
load : in std_logic;
shift : in std_logic;
din : in std_logic_vector(N-1 downto 0);
dout : out std_logic_vector(N-1 downto 0);
serin : in std_logic;
serout: out std_logic);
end shift_reg_full;
architecture a of shift_reg_full is
signal q : std_logic_vector(N-1 downto 0);
begin
process(clk, rst_n)
begin
if rst_n = '0' then
q <= (others => '0');
elsif clk'event and clk='1' then
if load = '1' then
q <= din;
elsif shift='1' then
q <= q(N-2 downto 0) & serin;
end if;
end if;
end process;
serout <= q(N-1) after del;
dout <= q after del;
end;