LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity sort2 is
generic(Nbits : Natural := 8;
Nidx : Natural := 4);
port(
dat0i : in std_logic_vector(Nbits+Nidx-1 downto 0);
dat1i : in std_logic_vector(Nbits+Nidx-1 downto 0);
dat0o : out std_logic_vector(Nbits+Nidx-1 downto 0);
dat1o : out std_logic_vector(Nbits+Nidx-1 downto 0));
end sort2;
architecture a of sort2 is
signal d0gtd1 : std_logic;
signal dat0cmp, dat1cmp : std_logic_vector(Nbits-1 downto 0);
begin
dat0cmp <= dat0i(Nbits+Nidx-1 downto Nidx);
dat1cmp <= dat1i(Nbits+Nidx-1 downto Nidx);
d0gtd1 <= '1' when dat0cmp > dat1cmp else '0';
dat0o <= dat0i when d0gtd1 = '1' else dat1i;
dat1o <= dat1i when d0gtd1 = '1' else dat0i;
end;