LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity sort4 is generic(Nbits : Natural := 8; Nidx : Natural := 2; ipipe : Boolean := false; mpipe : Boolean := false; opipe : Boolean := false); port( clk : in std_logic; dat0i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat1i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat2i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat3i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat0o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat1o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat2o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat3o : out std_logic_vector(Nbits+Nidx-1 downto 0)); end sort4; architecture struct of sort4 is component dff_array is generic (N : Natural := 4); port ( clk : in std_logic; d : in std_logic_vector(N-1 downto 0); q : out std_logic_vector(N-1 downto 0) ); end component; component sort2 is generic(Nbits : Natural := 8; Nidx : Natural := 4); port( dat0i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat1i : in std_logic_vector(Nbits+Nidx-1 downto 0); dat0o : out std_logic_vector(Nbits+Nidx-1 downto 0); dat1o : out std_logic_vector(Nbits+Nidx-1 downto 0)); end component; signal dat0s , dat1s , dat2s , dat3s : std_logic_vector(Nbits+Nidx-1 downto 0); signal dat0o1, dat1o1, dat2o1, dat3o1 : std_logic_vector(Nbits+Nidx-1 downto 0); signal dat0m , dat1m , dat2m , dat3m : std_logic_vector(Nbits+Nidx-1 downto 0); signal dat1o2, dat2o2 : std_logic_vector(Nbits+Nidx-1 downto 0); signal dat0o3, dat1o3, dat2o3, dat3o3 : std_logic_vector(Nbits+Nidx-1 downto 0); signal dat1o4, dat2o4 : std_logic_vector(Nbits+Nidx-1 downto 0); begin ip1: if ipipe generate ir0: dff_array generic map(N => dat0i'length) port map( clk => clk, d => dat0i, q => dat0s); ir1: dff_array generic map(N => dat1i'length) port map( clk => clk, d => dat1i, q => dat1s); ir2: dff_array generic map(N => dat2i'length) port map( clk => clk, d => dat2i, q => dat2s); ir3: dff_array generic map(N => dat3i'length) port map( clk => clk, d => dat3i, q => dat3s); end generate; nip1: if not ipipe generate dat0s <= dat0i; dat1s <= dat1i; dat2s <= dat2i; dat3s <= dat3i; end generate; u1u : sort2 generic map(Nbits => Nbits, Nidx => Nidx) port map( dat0i => dat0s, dat1i => dat1s, dat0o => dat0o1, dat1o => dat1o1); u1d : sort2 generic map(Nbits => Nbits, Nidx => Nidx) port map( dat0i => dat2s, dat1i => dat3s, dat0o => dat2o1, dat1o => dat3o1); u2m : sort2 generic map(Nbits => Nbits, Nidx => Nidx) port map( dat0i => dat1o1, dat1i => dat2o1, dat0o => dat1o2, dat1o => dat2o2); mp1: if mpipe generate mr0: dff_array generic map(N => dat0i'length) port map( clk => clk, d => dat0o1, q => dat0m); mr1: dff_array generic map(N => dat1i'length) port map( clk => clk, d => dat1o2, q => dat1m); mr2: dff_array generic map(N => dat2i'length) port map( clk => clk, d => dat2o2, q => dat2m); mr3: dff_array generic map(N => dat3i'length) port map( clk => clk, d => dat3o1, q => dat3m); end generate; nmp1: if not mpipe generate dat0m <= dat0o1; dat1m <= dat1o2; dat2m <= dat2o2; dat3m <= dat3o1; end generate; u3u : sort2 generic map(Nbits => Nbits, Nidx => Nidx) port map( dat0i => dat0m, dat1i => dat1m, dat0o => dat0o3, dat1o => dat1o3); u3d : sort2 generic map(Nbits => Nbits, Nidx => Nidx) port map( dat0i => dat2m, dat1i => dat3m, dat0o => dat2o3, dat1o => dat3o3); u4m : sort2 generic map(Nbits => Nbits, Nidx => Nidx) port map( dat0i => dat1o3, dat1i => dat2o3, dat0o => dat1o4, dat1o => dat2o4); op1: if opipe generate or0: dff_array generic map(N => dat0o3'length) port map( clk => clk, d => dat0o3, q => dat0o); or1: dff_array generic map(N => dat0o3'length) port map( clk => clk, d => dat1o4, q => dat1o); or2: dff_array generic map(N => dat0o3'length) port map( clk => clk, d => dat2o4, q => dat2o); or3: dff_array generic map(N => dat0o3'length) port map( clk => clk, d => dat3o3, q => dat3o); end generate; nop1: if not opipe generate dat0o <= dat0o3; dat1o <= dat1o4; dat2o <= dat2o4; dat3o <= dat3o3; end generate; end;