LIBRARY
IEEE
;
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
entity
xor3
is
port
(
a0
:
in
std_logic
;
a1
:
in
std_logic
;
a2
:
in
std_logic
;
y
:
out
std_logic
);
end
xor3
;
architecture
a
of
xor3
is
begin
y
<=
a0
xor
a1
xor
a2
;
end
;