`define use_aggr `define out_reg `ifdef out_reg module adder(clk, a, b, cin, y, cout); `else module adder(a, b, cin, y, cout); `endif parameter N = 8; `ifdef out_reg input clk; `endif input cin; input [N-1:0] a, b ; output cout; output [N-1:0] y; wire [N-1:0] yi; wire couti; `ifdef out_reg reg cout; reg [N-1:0] y; `endif `ifdef use_aggr assign {couti, yi} = cin + a + b; `else wire [N:0] sum; assign sum = cin + a + b; assign yi = sum[N-1:0]; assign couti = sum[N]; `endif `ifdef out_reg always @(posedge clk) begin cout <= couti; y <= yi; end `else assign cout = couti; assign y = yi; `endif endmodule