`timescale 1 ns / 1 ns
module counter(clk, cnten, rst_n, d, sload, q, co);
parameter del = 10;
parameter N = 4;
input clk, cnten, rst_n, sload;
input [N-1:0] d;
output co;
output [N-1:0] q;
reg [N-1:0] q_i;
always @(posedge clk)
begin
if (rst_n == 0) q_i <= 0;
else
if (sload == 1) q_i <= d;
else
if (cnten == 1) q_i <= q_i + 1'b1;
end
assign # del co = (& q_i) & (~sload) & cnten;
assign # del q = q_i;
endmodule