module demux(I, SEL, Y); parameter Nbit = 3; parameter Nout = 1 << Nbit; input [Nbit-1:0] SEL; input I; output [Nout-1 : 0] Y; reg [Nout-1:0] Y; always @(I or SEL) begin Y = 0; Y[SEL] = I; end endmodule