module
dffe
(
d
,
clk
,
ce
,
qfd
,
qfde
);
input
d
,
clk
,
ce
;
output
qfd
,
qfde
;
reg
qfd
,
qfde
;
always
@(
posedge
clk
)
begin
qfd
<=
d
;
end
always
@(
posedge
clk
)
begin
if
(
ce
==
1
)
qfde
<=
d
;
end
endmodule