module filt_shortv(clk, d, q);
parameter N = 3;
input clk, d;
output q;
reg [N-1:0] samples;
reg q;
wire all_high, all_low_n;
assign all_high = & samples;
assign all_low_n = | samples;
always @(posedge clk)
begin
samples <= {samples[N-2:0], d};
q <= (q | all_high) & all_low_n;
end
endmodule