module
latches
(
d
,
clk
,
aclr
,
qldc
,
qld
);
input
d
,
clk
,
aclr
;
output
qldc
,
qld
;
reg
qldc
,
qld
;
always
@(
clk
or
d
)
begin
if
(
clk
==
1
)
qld
<=
d
;
end
always
@(
clk
or
aclr
or
d
)
begin
if
(
aclr
==
1
)
qldc
<=
0
;
else
if
(
clk
==
1
)
qldc
<=
d
;
end
endmodule