module mux21_nbit_wor(I0, I1, SEL, Y);
parameter N = 2;
input [N-1:0] I0, I1;
input SEL;
output [N-1:0] Y;
wor [N-1:0] Y;
wire [N-1:0] I0g, I1g;
assign I0g = (SEL==0) ? I0 : 0;
assign I1g = (SEL==1) ? I1 : 0;
assign Y = I0g;
assign Y = I1g;
endmodule