module prior_assign(irq, valid, irq_no);
input [3:0] irq;
output valid;
output [1:0] irq_no;
wire valid;
wire [1:0] irq_no;
assign valid = | irq;
assign irq_no = (irq[3]==1) ? 2'd3 :
(irq[2]==1) ? 2'd2 :
(irq[1]==1) ? 2'd1 :
(irq[0]==1) ? 2'd0 : 2'bxx;
endmodule