module prior_casex(irq, valid, irq_no);
input [3:0] irq;
output valid;
output [1:0] irq_no;
reg [1:0] irq_no;
reg valid;
always @(irq)
begin
irq_no <= 2'bxx;
valid <= 1'b1;
casex (irq)
4'b1xxx : irq_no <= 2'd3;
4'b01xx : irq_no <= 2'd2;
4'b001x : irq_no <= 2'd1;
4'b0001 : irq_no <= 2'd0;
4'b0000 : valid <= 1'b0;
default : valid <= 1'bx;
endcase
end
endmodule