module
psrg_gen
(
clk
,
load
,
din
,
q
);
parameter
N
=
4
;
input
clk
,
load
;
input
[
N
-
1
:
0
]
din
;
output
[
N
-
1
:
0
]
q
;
`include
"psrg_func.v"
reg
[
N
-
1
:
0
]
q
;
always
@(
posedge
clk
)
begin
if
(
load
==
1
)
q
<=
din
;
else
q
<=
{
q
[
N
-
2
:
0
],
psrg_func
(
N
,
q
)};
end
endmodule