`timescale 1 ns / 1 ns module regfile(clk, rst_n, we, din, waddr, raddra, raddrb, rdata, rdatb); parameter Na = 2; parameter Nd = 3; input clk, rst_n, we; input [Na-1:0] waddr, raddra, raddrb; input [Nd-1:0] din; output [Nd-1:0] rdata, rdatb; // localparam Nr = 1 << Na; // not accepted by all tools! parameter Nr = 1 << Na; reg [Nd-1:0] rf_data [0:Nr-1]; reg [0:Nr-1] we_dec; integer i; // the decoder always @(we or waddr) begin we_dec <= 0; we_dec[waddr] <= we; end // the registers always @(posedge clk) for (i = 0; i < Nr; i = i + 1) if (rst_n == 0) rf_data[i] <= 0; else if (we_dec[i]==1) rf_data[i] <= din; // two read muxes assign rdata = rf_data[raddra]; assign rdatb = rf_data[raddrb]; endmodule