`timescale 1 ns / 1 ns
module shift_reg_var(clk, d, q);
input clk, d;
output q;
reg a, b, c;
always @(posedge clk) a = d;
always @(posedge clk) b = a;
always @(posedge clk) c = b;
assign q = c;
endmodule
module shift_reg_var_ok(clk, d, q);
input clk, d;
output q;
reg a, b, c;
always @(posedge clk)
begin
c = b;
b = a;
a = d;
end
assign q = c;
endmodule