module state_2phv(clk, rst_n, P1, P2, EN, UP);
input clk;
input rst_n;
input P1;
input P2;
output EN;
output UP;
parameter S00 = 2'b00, S01 = 2'b01, S10 = 2'b10, S11 = 2'b11;
reg [1:0] present_st;
reg [1:0] next_st;
reg [1:0] p12s;
reg p1s, p2s;
reg EN, UP;
always @(present_st or p1s or p2s)
begin
EN <= 2'b0; // the default is no counting
UP <= 1'bx; // in this case the UP is don't care
// the outputs are active only when doing a state transition
next_st <= present_st;
case (present_st)
S00: if (p1s == 1'b1) begin
next_st <= S10; EN <= 1'b1; UP <= 1'b0;
end
else if (p2s == 1'b1) begin
next_st <= S01; EN <= 1'b1; UP <= 1'b1;
end
S01: if (p1s == 1'b1) begin
next_st <= S11; EN <= 1'b1; UP <= 1'b1;
end
else if (p2s == 1'b0) begin
next_st <= S00; EN <= 1'b1; UP <= 1'b0;
end
S11: if (p1s == 1'b0) begin
next_st <= S01; EN <= 1'b1; UP <= 1'b0;
end
else if (p2s == 1'b0) begin
next_st <= S10; EN <= 1'b1; UP <= 1'b1;
end
S10: if (p1s == 1'b0) begin
next_st <= S00; EN <= 1'b1; UP <= 1'b1;
end
else if (p2s == 1'b1) begin
next_st <= S11; EN <= 1'b1; UP <= 1'b0;
end
default : next_st <= 2'bxx;
endcase
end
always @(posedge clk)
begin
p1s <= P1; // synchronize the inputs
p2s <= P2; // to the Mealy machine!
p12s = {p1s, p2s};
if (rst_n == 1'b0) // jump to the correct state
case (p12s)
S00 : present_st <= S00;
S01 : present_st <= S01;
S10 : present_st <= S10;
S11 : present_st <= S11;
default : present_st <= 2'bxx;
endcase
else
present_st <= next_st; // store the next state
end
endmodule